1. Technical Field of the Invention
The present invention relates to a liquid crystal display apparatus using a so-called unified memory architecture (UMA), which shares a display memory and a memory for storing execution code and data for a CPU. More particularly, the present invention relates to a liquid crystal display apparatus that adopts a UMA as a display memory of a device that transfers display data to the liquid crystal display panel.
2. Conventional Technology
There are some conventional liquid crystal display apparatuses that use a UMA structure as shown in FIG. 1, but they have to transfer display data in synchronism with refreshing of the liquid crystal display, and therefore occupy a band of the bus connected to the UMA memory to some degree. An arrow shown in FIG. 1 indicates a flow of data relating to display.
A CPU 1 uses a UMA memory 3 for executing a program and also as an area for storing display data. A liquid crystal controller 5 accesses the UMA memory 3 through a CPU interface 2 to read out display data, and transfers the same to a liquid crystal line driving driver 7. A liquid crystal panel 9 performs a display operation using the line driver 7 and a common driver 8.
In this instance, the liquid crystal controller 5 must write data in synchronism with a timing required by the line driver 7. For memory accesses for display, a memory bus 4 is used just as does the CPU and other bus masters. However, unless the display is given a first priority, the display flickers, and therefore the CPU and other bus masters are put in a standby state. Such timing is shown in FIG. 2.
A timing chart 20 indicates periods in which the CPU 1 can access the UMA memory 3. A timing chart 21 indicates timings in which the liquid crystal controller 5 makes periodical accesses to the UMA memory 3. When the liquid crystal display is refreshed at 50 Hz, accesses to the display data occurs at 20 nm intervals. As a result, the period in which the CPU 1 can access to the UMA memory 3 are divided into segments.
In other words, in a display apparatus using a conventional UMA memory, the bandwidth used by the CPU and other band masters is restricted, and the operation of an application in which frequent memory accesses are made, such as in a process of moving pictures, is often hindered.
It is an object of the present invention to reduce the influence of reduction of bandwidth of a memory bus, effectively perform a display operation and reduce the overall power consumption for the display operation.